The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for connecting a buffered automated flash controller directly to a processor memory bus.
A solid-state drive (SSD) is a data storage device that uses solid-state memory to store persistent data with the intention of providing access in the same manner of a traditional block I/O hard disk drive. SSDs are distinguished from traditional hard disk drives (HDDs), which are electromechanical devices containing spinning disks and movable read/write heads. SSDs, in contrast, use microchips that retain data in non-volatile memory chips and contain no moving parts. Compared to electromechanical HDDs, SSDs are typically less susceptible to physical shock, are quieter, and have lower access time and latency. However, many SSDs use the same interface as hard disk drives, such as serial attached SCSI (SAS), serial advanced technology attachment (SATA), and Fibre Channel, thus allowing both HDDs and SSDs to be used in the same enclosure and allowing applications to seamlessly take advantage of either. Using interfaces designed for HDDs results in added latency from several sources. First of all, if the SSD is out in the SAN, there are SAN fabric delays, and delays by the external storage controller for directory lookups and the like. For SSDs present on the PCI Express link, the most significant form of latency is actually software latency to go through the software driver and then wait for the DMA to complete and to process the completion status.
Some SSDs may be attached to peripheral component interconnect express (PCIe) interfaces. This is an effective way to reduce latency. Because non-volatile memories used in SSDs, i.e., Flash memories, are block oriented and require erases before they can be written to, software drivers use HDD access methods to write and read data. This involves building a scatter/gather list and sending control blocks to the PCIe card to tell the SSD where to fetch data and then completion status must be sent to the driver that the operation is finished. This method of interface results in significant added latency to build the scatter gather lists, send the command to the storage device, wait for the DMA to complete and finally the ending status.